Design and analysis of high performance multistage interconnection networks

Abstract

Small switching elements are the key components of multistage interconnection networks (MINS) used in multiprocessors and in high speed switching fabrics for broad-band communication systems. The structure of their internal buffers, efficient design and utilization of the clock period are crucial factors in determining their performance. We begin with the study of various buffer allocation schemes that include m queue buffers with static and dynamic buffer allocation. The dynamic buffer allocation has the ability to adapt to variations in traffic patterns and are, therefore, shown to offer higher throughput and lower latency compared to static buffers. We prop a new buffer design, called dynamically allocated fully connected buffer, and s that it outperforms the existing designs. The applications considered to evaluate the buffer allocation schemes are asynchronous traffic that include data transmission and soft real time traffic that include voice and video. The advantages of non- Fl message selection over FIFO selection are also studied. Another important issue is the clock design in synchronous networks. The existing models assume that the clock period consists of two parts. The control messages are transferred between switching stages during the first part, and the actual d transfer takes place during the second part. We propose a new control design single queue MINs that reduces the duration of the clock period by making use output buffers and acknowledgments. We develop an analytical model to compare its performance with the existing designs reported in the literature. We validate on model with extensive simulation studies. Index Terms - Multistage interconnection networks, packet switching, static buffer allocation, dynamic buffer allocation, non-FIFO packet selection, soft real time traffic, performance analysis, throughput, delay, clock cycle.