A wafer-scale boundary value integrated circuit architecture

Abstract

Wafer-Scale Integration (WSI) technology offers the potential for improving speed and reliability of a large integrated circuit system. An architecture is presented for a boundary value integrated circuit engine which lends itself to implementation in WSI. The philosophy underpinning this architecture includes local communication, cell regularity, and fault tolerance. The research described here proposes, investigates, and simulates this computer architecture and its flaw avoidance schemes for a WSI implementation. Boundary value differential equation computations are utilized in a number of scientific and engineering applications. A boundary value machine is ideally suited for solutions of finite difference and finite element problems with specified boundary values. The architecture is a 2-D array of computational cells. Each basic cell has four bit serial processing elements (PEs) and a local memory. Most communication is limited to transfer between adjacent PEs to reduce complexity, avoid long delays, and localize the effects of silicon flaws. Memory access time is kept short by restricting memory service to PEs in the same cell. I/O operation is performed by means of a row multiple single line I/O bus, which allows fast, reliable and independent data transference. WSI yield losses are due to gross defects and random defects. Cross defects which affect large portions of the wafer are usually fatal for any WSI implementation. Overcoming random defects which cover either a small area or points is achieved by defect avoidance schemes that are developed for this architecture. Those schemes are provided at array, cell, and communication level. Capabilities and limitations of the proposed WSI architecture can be observed through the simulations. Speed degradation of the array and the PE due to silicon defects is observed by means of simulation. Also, module and bus utilization are computed and presented.