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dc.contributor.advisorNoe, P. S.
dc.creatorSuraratrungsi, Songsuk
dc.date.accessioned2020-08-21T21:34:57Z
dc.date.available2020-08-21T21:34:57Z
dc.date.issued1977
dc.identifier.urihttps://hdl.handle.net/1969.1/DISSERTATIONS-365728
dc.descriptionVita.en
dc.description.abstractThe feasibility of a microprocessor implementation as a part of a low-cost GPS receiver is described. A noisy model is considered in the dynamic system simulation consisting of a C5A flight from California to Hawaii with the GPS satellite pseudo-range inputs. A total of 726 fixes are taken during a 6-hour flight with an RMS error of 31*59 ft. and a fix rate of 30 s/fix. A complete 32 bit floating point math package was developed for the Intel 8080 microprocessor in order to implement the navigation algorithm.en
dc.format.extentvii, 52 leavesen
dc.format.mediumelectronicen
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.rightsThis thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use.en
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/
dc.subjectArtificial satellites in navigationen
dc.subjectMicroprocessorsen
dc.subjectMajor electrical engineeringen
dc.subject.classification1977 Dissertation S961
dc.subject.lcshMicroprocessorsen
dc.subject.lcshArtificial satellites in navigationen
dc.titleAn Intel 8080 microprocessor implementation of a navigation algorithm for the low-cost GPS receiveren
dc.typeThesisen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameDoctor of Philosophyen
dc.type.genredissertationsen
dc.type.materialtexten
dc.format.digitalOriginreformatted digitalen
dc.publisher.digitalTexas A&M University. Libraries
dc.identifier.oclc3477847


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