A VLSI Cache RISC for the C language

Abstract

The performance of computers has always been the major concern of computer architects and circuit designers. Besides their advantages of ease of design and reliability, the RISCs (Reduced Instruction Set Computers) have been able to outperform many existing computers built upon the conventional CISC (Complex Instruction Set Computer) philosophy, without the loss of high-level language support. This research presents an architectural support for a RISC in which an on-chip cache is utilized. Due to the rapidly expanding capabilities of VLSI (Very Large-Scale Integration) microelectronic circuits, a cache memory of considerable amount of storage can be embeded in the same silicon chip of the RISC CPU (central processing unit), which may greatly enhance the communications ability and access speed between the RISC and the main memory. As a result of this research, great performance improvements can be expected with the presence of the on-chip cache, and the cache does pay off for the silicon area it occupies. The implication of this research is nevertheless straightforward. It provides a basis for the VLSI design and implementation of computer systems which break away from the traditional computer architectures: Better performance can be obtained through the incorporation of supporting peripherals or special-purpose hardware on the microprocessor chip if properly designed, and the many ordinary communications and interface bottlenecks between the CPU and the peripherals can be resolved. The major accomplishment of this research may be more than the conception of a high-performance, 22-instruction Cache RISC: As semiconductor technology continues to pursue the scaling down of IC (integrated circuit) device dimensions, this research suggests the implementation of multi-components of a computer system onto a single chip as an alternative of speeding up, rather than unduly increasing the C PU manipulation power.