Reconfigurable computer systems for wafer scale integration

Abstract

This dissertation present new approaches for testing and reconfiguring several types of wafer-scale integration computer systems. Chapter II examines a fault tolerant scheme for two-dimensional arrays of processors which conceptually reconfigures the array without the use of spare rows or columns. Reconfiguration approaches with different neighbor connected processor interconnection networks are proposed. Also, three approaches are proposed for mapping image data to and from the array, depending on the type of array and computational power available in each processing element. The proposed reconfiguration approaches have been emulated on a 32 $times$ 64 processor MasPar computer. Chapter III presents a new fault-tolerant approach for performing rank order filtering. This approach is based on offsetting the loss of one or more faulty processors using the available fault-free processors. The proposed approach consists of bypassing the faulty processing elements in the array and using the available connections to compute the rank of the image pixels on the accessible pixel values. A parallel algorithm which is applicable to this fault-tolerant procedure, is proposed with a time complexity of O(N), where N is the dimension of the array. Chapter IV presents a new algorithm for reconfiguring WSI/VLSI multipipeline arrays in the presence of faults in links, processing elements (PEs) and switching elements (SEs). Reconfiguration is accomplished under a fault model in which a PE and link can be either fault-free or faulty and a SE is modeled by relating its switching capabilities to its status and the status of the connecting links. An algorithm which maximizes the number of reconfigured pipelines, is proposed; this algorithm has an execution complexity lower than a previous algorithm.