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dc.contributor.advisorBliss, William G.
dc.creatorSetty, Palaksha A.
dc.description.abstractFlash conversion remains a necessary choice for high-speed Analog-to-Digital (A/D) conversion, despite its many disadvantages. Such conversion, by nature, involves 2^N sampling elements for an N bit converter. The differences in the signal delays to each of these sampling elements results in sampling the wrong value of the input, and gives rise to a systematic voltage error in a sequence of sampled voltages. The mechanisms that give rise to such delay differences, normally referred to as dynamic errors, are analyzed. Converter's dynamic performance in the presence of these errors is simulated using high level simulations. Simulating the converter's dynamic behavior, expressed as its Signal-to-Noise plus Distortion ratio (SNDR), using accurate timing simulators such as SPICE, is known to be computationally intensive. Furthermore, such simulations do not necessarily incorporate all of the dynamic errors in the converter. A methodology is presented herein, where the converter's dynamic performance is simulated without excessive CPU time. All of the dynamic errors in the converter are lumped into a single effective timing error of the sampling clock. The timing error is a function of the input signal dynamics as well as the physical layout of the converter. An 8-bit Flash converter, with practical layout and circuits, is taken as an example, and its dynamic performance is simulated using this methodology. Computer usage time on the order of a few hours has been achieved with this methodology to obtain the SNDR of the converter. The accuracy of the simulation is expected to be comparable to that of SPICE. Testing the dynamic performance of high-speed converters requires function generators with a linearity better than that of the converter under test. A novel compensation algorithm is presented which allows one to test the converter using function generators with nonlinearities comparable to or larger than those in the converter. The algorithm uses two sets of measurements: one set taken with the function generator and the A /D converter, and another taken with an all-pass filter inserted between the function generator and the A/D converter. Simulation results indicate that A/D converters with a SNDR of 60-70dB can be measured with an absolute accuracy of better than 0.2dB using a function generator that has ~40dB distortion components.en
dc.format.extentxiii, 96 leavesen
dc.rightsThis thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use.en
dc.subjectMajor electrical engineeringen
dc.subject.classification1992 Dissertation S495
dc.subject.lcshAnalog-to-digital convertersen
dc.subject.lcshAnalog-to-digital convertersen
dc.subject.lcshMathematical modelsen
dc.titleDynamic accuracy considerations in Flash A/D convertersen
dc.typeThesisen A&M Universityen of Philosophyen Den
dc.contributor.committeeMemberBryant, Jack D.
dc.contributor.committeeMemberSanchez-Sinencio, Edger
dc.contributor.committeeMemberWatson, Karan L.
dc.format.digitalOriginreformatted digitalen
dc.publisher.digitalTexas A&M University. Libraries

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