Investigation of Four Circuit Designs for Mutlivalued Logic Applications

Abstract

Multivalued logic (MVL) circuits display more than the two states (LOW and HIGH) exhibited by traditional logic circuits. A ternary logic circuit, for example, may contain states such as HIGH, MEDIUM, and LOW. The demands of low power loss and higher device speed have prompted circuit designers to consider MVL. This thesis begins with a design that employs CMOS inverters (with different PMOS and NMOS threshold voltages) connected in parallel. The design was successfully simulated using PSPICE; the voltage transfer characteristics clearly show three states. HSPICE simulations using MOSIS parameters were not successful; three-state characteristics were not seen when using the identical circuit simulated by PSPICE. A discussion on the differences between PSPICE and HSPICE is included. Other circuit designs will also be analyzed including (1) a circuit that uses NMOS transistors to model the characteristics of switches; (2) a revised circuit that uses diode-connected transistors to replace resistors included in the previous design; and (3) a circuit that replaces two large resistances with two PMOS transistors. While the parallel-inverter design consists of four transistors (for three states), the other designs include circuits with (1) four resistors and two transistors; (2) two resistors and four transistors; and (3) six transistors. Simulations done using PSPICE and HSPICE software packages show promise for using the designs as MVL circuits.