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dc.contributor.advisorHu, Jiang
dc.creatorKim, Min-seok
dc.date.accessioned2006-08-16T19:06:29Z
dc.date.available2006-08-16T19:06:29Z
dc.date.created2003-05
dc.date.issued2006-08-16
dc.identifier.urihttps://hdl.handle.net/1969.1/3856
dc.description.abstractThis thesis studies the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. Although the number of constraints is reduced, the problem becomes more difficult to solve due to the enlarged solution space. Perhaps, the only previous study used a very primitive delay model which could not handle difficult instances when sink groups are intermingled. We reuse existing techniques to solve this problem including difficult instances based on an improved delay model. Experimental results show that our algorithm can reduce the total clock routing wirelength by 9%–15% compared to greedy-DME, which is one of the best zero skew routing algorithms.en
dc.format.extent108149 bytesen
dc.format.mediumelectronicen
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherTexas A&M University
dc.subjectclock routingen
dc.titleAssociative skew clock routing for difficult instancesen
dc.typeBooken
dc.typeThesisen
thesis.degree.departmenten
thesis.degree.disciplineComputer Engineering (CEEN)en
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberKim, Eun Jung
dc.contributor.committeeMemberShi, Weiping
dc.type.genreElectronic Thesisen
dc.type.materialtexten
dc.format.digitalOriginborn digitalen


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