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dc.contributor.advisorWalker, Duncan
dc.creatorSabade, Sagar Suresh
dc.date.accessioned2004-09-30T01:48:59Z
dc.date.available2004-09-30T01:48:59Z
dc.date.created2005-05
dc.date.issued2004-09-30
dc.identifier.urihttp://hdl.handle.net/1969.1/267
dc.description.abstractSemiconductor manufacturers must ensure that chips conform to their specifications before they are shipped to customers. This is achieved by testing various parameters of a chip to determine whether it is defective or not. Separating defective chips from fault-free ones is relatively straightforward for functional or other Boolean tests that produce a go/no-go type of result. However, making this distinction is extremely challenging for parametric tests. Owing to continuous distributions of parameters, any pass/fail threshold results in yield loss and/or test escapes. The continuous advances in process technology, increased process variations and inaccurate fault models all make this even worse. The pass/fail thresholds for such tests are usually set using prior experience or by a combination of visual inspection and engineering judgment. Many chips have parameters that exceed certain thresholds but pass Boolean tests. Owing to the imperfect nature of tests, to determine whether these chips (called "outliers") are indeed defective is nontrivial. To avoid wasted investment in packaging or further testing it is important to screen defective chips early in a test flow. Moreover, if seemingly strange behavior of outlier chips can be explained with the help of certain process parameters or by correlating additional test data, such chips can be retained in the test flow before they are proved to be fatally flawed. In this research, we investigate several methods to identify true outliers (defective chips, or chips that lead to functional failure) from apparent outliers (seemingly defective, but fault-free chips). The outlier identification methods in this research primarily rely on wafer-level spatial correlation, but also use additional test parameters. These methods are evaluated and validated using industrial test data. The potential of these methods to reduce burn-in is discussed.en
dc.format.extent6428010 bytesen
dc.format.extent318165 bytesen
dc.format.mediumelectronicen
dc.format.mimetypeapplication/pdf
dc.format.mimetypetext/plain
dc.language.isoen_US
dc.publisherTexas A&M University
dc.subjectOutlier identificationen
dc.subjectIDDQen
dc.subjectSpatial correlationen
dc.subjectParametric testen
dc.titleIntegrated circuit outlier identification by multiple parameter correlationen
dc.typeBooken
dc.typeThesisen
thesis.degree.departmentComputer Scienceen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameDoctor of Philosophyen
thesis.degree.levelDoctoralen
dc.contributor.committeeMemberSarin, Vivek
dc.contributor.committeeMemberFriesen, Donald
dc.contributor.committeeMemberTaylor, Henry
dc.type.genreElectronic Dissertationen
dc.type.materialtexten
dc.format.digitalOriginborn digitalen


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