High Bandwidth Interposer Switch (HBI-S) Topology in Modular System on Chip

Abstract

Systems on Chip (SoCs) are getting bigger and complex to achieve performance improvement. As it is costly to develop one gigantic chip, ideas of modular SoCs are proposed. It divides the SoC into small chiplets while interconnecting them with a silicon interposer. Modular SoCs are cheaper to develop while also providing flexible topologies and routing algorithms. They are also advantageous in terms of power and efficiency compared to the traditional SoCs. However, modular SoC has a deadlock issue when interconnecting the interposer with the chiplets. Remote Control (RC) is one of the techniques that can solve the deadlock problem. It places a buffer into the boundary routers with selective injection controls to avoid the deadlock from happening. RC was proven efficient with a mesh topology. However, the interposer network experiences a bottleneck and limits the potential performance benefit of the RC technique. We propose a High Bandwidth Interposer Switch (HBI-S) topology that improves the interposer network's bisection bandwidth compared to the mesh topology. It also significantly reduces the diameter of the interposer network. HBI-S topology achieved better saturation throughput than the mesh topology when simulating various synthetic traffic patterns through Booksim. Specifically, HBI-S topology showed about 2 times higher throughput in bit-complement, tornado, shuffle, and asymmetric traffic patterns. On average, HBI-S topology provides 1.73 times better throughput than mesh topology.