| dc.description.abstract | With more sensitive data being stored on computers, the cyber-attack risk is increasing globally. Therefore, it’s crucial to address security vulnerabilities before new threats emerge promptly and potentially cause significant harm in the future. Recently, Spectre and Meltdown attacks known as cache side-channel attacks exploit modern processor characteristics. Despite the seriousness of these attacks, they are under-researched and need more attention to safeguard our data.
This thesis addresses how to optimize and improve the ReViCe, the solution for mitigating vul-nerabilities of cache side-channel attacks, a problem caused by characteristics of modern proces-sors. ReViCe enables speculative loads to refresh caches ahead of time while saving any removed line within the victim cache. If mis-speculation occurs, the replaced lines from the victim cache can be returned to the cache for undoing the cache changes, which can effectively isolate the cache changes for protecting us against cache-based Spectre and Meltdown attacks.
We also introduce a more realistic, secure design for ReViCe. We enhance the security design by conducting experiments, tackling related work CacheRewinder, identifying the appropriate size of victim cache and buffer, and incorporating a deadlock-free algorithm. These changes allow us to implement a safer and more practical version of ReViCe, requiring less memory. | |
