Cross-Layer Age-Aware Scheme for Reliable Memristor Crossbar Accelerator Design

Abstract

Memristor crossbars (MC) are being widely adopted in research for energy-efficient deep learning (DL) due to their low power and fast switching characteristics, and nonvolatile nature. In particular, MCs have been demonstrated as an excellent vector-matrix multiplication engine. However, MCs encounter severe reliability challenges due to the aging of their memory cells. The major contributor to MC’s aging in deep learning applications is the frequent weight updates. During a weight update operation, target cells in an MC are written with new conductance values. Over time, cells degrade (called aging) and hence, their written conductance values differ from the target value in each weight-update cycle. As a result, aging drastically impacts the overall performance of MC-based deep learning thereby becoming a major obstacle to the commercial adoption of MCs. Limited attempts have been made to address this challenge. In this work, we introduce a centralized online test framework to locate aged cells in a crossbar. Experiments with standard CAD tools in conjunction with an established deep learning framework show an average of 85% success rate in identifying aged cells in the crossbar. We also introduce an age-aware mapping scheme that significantly reduces the percentage of erroneous cells. We also test another approach where we clip the number of allowable resistance states to a range not affected by aging. This approach seems to be suitable for fully analog circuitry and also consumes less power.