A Mixed-Mode Low-Dropout Regulator with Ultra-Low Quiescent Current and Fast Transient Response

Abstract

The popularity of portable devices, such as smart phones, smart watches, laptops, tablets, and internet of things (IoT) devices has continually increased in recent years. These devices often need dedicated, rechargeable batteries and local power management systems to be considered fully portable. Since these devices continue to shrink in size, it has become necessary to design most of the electronics in these devices as integrated circuits (ICs). Furthermore, since ICs require regulated power supplies, the design of fully integrated power management systems has developed into a popular area of research. Typical power management systems consist of a DC-DC switching regulator that boosts or bucks the battery voltage to the appropriate level followed by a low-dropout regulator (LDO) that helps remove unwanted supply ripple. Since many high-performing, noise-sensitive circuits cannot tolerate the presence of supply ripple, the LDO has become an essential component. Recent research in LDO design has focused on the integration of the load capacitors on chip. Thus, “capacitorless” LDOs, where the output capacitor is small enough to be placed on chip, have become a popular space-saving alternative to traditional LDOs. In addition, power efficiency is a major focus in LDO design since many portable systems are designed to maximize battery life. LDOs also need to respond quickly to changing load conditions, but traditional analog topologies are often slower than desired. Therefore, fast, digital LDO implementations have be-come a practical alternative. However, digital LDOs add a steady-state voltage ripple at the output of the system, which is not ideal. Thus, the focus of this thesis is to present research focusing on combining the strengths of analog and digital LDOs in a mixed-mode architecture. Furthermore, the system designed is capacitorless/fully integrated and additionally emphasizes high current efficiency. The system designed for this thesis uses a total of three loops working to regulate the output of the LDO. The first loop is a low-power analog LDO active at all times and regulates the loop alone when the load demands low current (i.e. less than 2mA). The second loop is a digital LDO with the current digital-to-analog converter (IDAC) operated in the saturation region. The final loop is a high-power analog LDO that supports up to 30mA of current and accounts for the quantization error of the digital LDO, removing the output ripple. Overall, the system is designed to quickly respond to load transients while maintaining high efficiency all while using an integrated output capacitor.