dc.contributor.advisor | Walker, Duncan M | |
dc.creator | Chakraborty, Avijit | |
dc.date.accessioned | 2023-02-07T16:12:49Z | |
dc.date.available | 2023-02-07T16:12:49Z | |
dc.date.created | 2022-05 | |
dc.date.issued | 2022-04-04 | |
dc.date.submitted | May 2022 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/197241 | |
dc.description.abstract | The electronic industry has evolved at a mindboggling pace over the last five decades. Moore’s Law [1] has enabled the chip makers to push the limits of the physics to shrink the feature sizes on Silicon (Si) wafers over the years. A constant push for power-performance-area (PPA) optimization has driven the higher transistor density trends. The defect density in advanced process nodes has posed a challenge in achieving sustainable yield. Maintaining a low Defect-per-Million (DPM) target for a product to be viable with stringent Time-to-Market (TTM) has become one of the most important aspects of the chip manufacturing process. Design-for-Test (DFT) plays an instrumental role in enabling low DPM. DFT however impacts the PPA of a chip. This research describes an approach of minimizing the scan test overhead in a chip based on circuit topology heuristics. These heuristics are applied on a full-scan design to convert a subset of the scan flip-flops (SFF) into D flip-flops (DFF). The K Longest Path per Gate (KLPG) [2] automatic test pattern generation (ATPG) algorithm is used to generate tests for robust paths in the circuit. Observability driven multi cycle path generation [3][4] and test are used in this work to minimize coverage loss caused by the SFF conversion process. The presence of memory arrays in a design exacerbates the coverage loss due to the shadow cast by the array on its neighboring logic. A specialized behavioral modeling for the memory array is required to enable test coverage of the shadow logic. This work develops a memory model integrated into the ATPG engine for this purpose. Multiple clock domains pose challenges in the path generation process. The inter-domain clocking relationship and corresponding logic sensitization are modeled in our work to generate synchronous inter-domain paths over multiple clock cycles. Results are demonstrated on ISCAS89 and ITC99 benchmark circuits. Power saving benefit is quantified using an open-source standard-cell library. | |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | |
dc.subject | Path Delay Test | |
dc.subject | ATPG | |
dc.subject | Scan Test | |
dc.subject | Memory Shadow Logic Test | |
dc.subject | Clock Domain Crossing | |
dc.title | Heuristics Based Test Overhead Reduction Techniques in VLSI Circuits | |
dc.type | Thesis | |
thesis.degree.department | Computer Science and Engineering | |
thesis.degree.discipline | Computer Engineering | |
thesis.degree.grantor | Texas A&M University | |
thesis.degree.name | Doctor of Philosophy | |
thesis.degree.level | Doctoral | |
dc.contributor.committeeMember | Mahapatra, Rabi N | |
dc.contributor.committeeMember | Liu, Jyh-Charn | |
dc.contributor.committeeMember | Hu, Jiang | |
dc.type.material | text | |
dc.date.updated | 2023-02-07T16:12:50Z | |
local.etdauthor.orcid | 0000-0002-1875-4957 | |