FPGA Acceleration for Random Forest Inference

Abstract

Random forest algorithm has been used broadly in both the research field and in the industry due to its ability to tackle both categorical and numerical dataset. FPGAs also have the highest growing potential and can be applied for the acceleration of random forest inference due to its low power consumption and parallelism support. Research have shown that a compact random forest algorithm is best executed through multi-threading and pipelining, and a FPGA implementation shows significant advantages compared to GP-GPU and CPU implementations in the area. It was able to process each decision tree within the forest independently in parallel. My research is dedicated to achieving this result by benchmarking individual performance running the same RF prediction algorithm on different platforms. The HDL code running on the FPGA will be translated from the source C++ code through Vitis HLS to be synthesized onto the FPGA board. The training data and the binary files will be processed beforehand for an equal competition for all platforms. I will be using various optimization techniques including loop unrolling and data-level parallelism to fully utilize the capabilities of FPGAs. With sufficient data and analysis, my result will show that FPGAs perform better compared to other platforms such as CPU or GP-GPU.