| dc.description.abstract | VLSI design productivity has already become the bottleneck to take full advantage of potential benefit brought by technology scaling, leading to the famous design productivity gap, i.e., the mismatch between the available transistor density and the transistor density that designers can handle. Advancement of VLSI design automation, or called EDA, is in urgent need to narrow down the gap.
The strong learning capability of modern machine learning (ML) techniques make them a good fit to cope with the high complexity in EDA tasks via discovering knowledge from past experience and applying them to new designs. However, it is extremely time consuming to obtain new training data from chip designs and existing data is usually noisy and disorganized. Thus, a main challenge faced by ML EDA is how to develop effective solutions with the poor quality data. Rather than plugin usage of existing ML techniques, it is necessary to customize ML methodologies for EDA tasks, mainly from three aspects: data, algorithm and domain knowledge, guided by insights into problem characteristics and understanding of ML methodologies.
We explore the potential of ML techniques in four representative EDA tasks as follows:
1. Design Rule Check (DRC) Hotspot Prediction: Design Rule Violation (DRV) prediction at early layout stages is critical to achieve freedom from DRV. We target at DRC hotspot prediction, i.e., classifying layout regions that are subject to DRVs, at cell placement stage without depending on global routing information. A customized convolutional network architecture is proposed to handle mixed resolution input and output.
2. DRC Heatmap Prediction: In this task we target at the DRV density regression prediction problem, which provides more detailed information in guiding DRV mitigation techniques than DRC hotspot prediction. Besides, the challenge of noisily labeled data caused by non-deterministic parallel routing is addressed by combining the strong modeling capability of deep neural networks and the strength of stochastic models in coping with uncertainty.
3. Routing-Free Crosstalk Prediction: Increasingly-smaller interconnect spacing in advanced technology nodes makes crosstalk a significant threat to signal integrity and timing. Given a placement, we identify physical, electrical and logical features that affect crosstalk-induced noise and delay. We then employ ML techniques to train the crosstalk prediction models, which can be used to identify crosstalk-critical nets at placement stages.
4. EDA Flow Parameter Tuning: We develop an automatic flow tuning tool for efficient parameter tuning of VLSI design flows. It utilizes both exploitation using transferred parameter knowledge from archived data from legacy designs and exploration via a multi-stage cooperative co-evolutionary framework. Furthermore, novel flow jump-start and early-stop techniques are developed to reduce the overall runtime for tuning. In addition, a concurrent multi-trade-off learning technique is proposed to enable truly multi-objective tuning by facilitating efficient Pareto front exploration.
The above are examples of customizing ML techniques for EDA problems and promising results have been achieved. We hope this dissertation can be instructive for further exploration in the direction of applying ML to EDA tasks. | |
