Design of a Highly Linear RF Front-End, a Low-Spur Fractional-N Frequency Synthesizer and a High-Speed, Low-Power Data Converter

Abstract

High-performance and low-power complementary metal-oxide-semiconductor (CMOS) circuit design techniques have been widely investigated both in industry and academia. For a 5G receiver, a wideband and linear RF front-end using minimal power is necessary. Meanwhile, a high-speed and low-power analog-to-digital converter (ADC) is needed to digitize the signal. The RF front-end and ADC need clock sources with low jitters and spurs to function properly.

A wideband and linear RF front-end is included in the first project. This front-end aimed at 3-6 GHz with a 200 MHz baseband bandwidth for 5G applications. A cross-coupled common-gate (CG) low noise transconductance amplifier (LNTA) with resistive degeneration was implemented to achieve linearity enhancement and noise reduction. A minimally-invasive filter enhanced out-of-band filtering. A 15.1 dBm input-referred third-order intercept point (IIP3) and a 3.0 dBm 1dB compression point (P1dB) over 3 to 6 GHz were demonstrated. The noise figure was less than 5.3 dB at 3 MHz offset. The power consumption was 69.6 mW.

The second project is a time-to-digital converter (TDC) assisted charge pump (CP) phase locked-loop (PLL) aiming at a 2.4-3.9 GHz output range with less than a −100 dBc reference spur and a −90 dBc out-of-band fractional spur. With the TDC, a charge pump with a 4-bit current digital-to-analog converter (DAC) was used to suppress the reference spurs. The digital phase processor filtered out the fractional spurs. Measured reference spur and out-of-band fractional spurs were −108 dBc and −95 dBc, respectively. The root mean square (rms) jitter was 247 fs in fractional-N mode. The power consumption was 15.94 mW at 3.3 GHz.

A 14-bit 1GS/s pipelined analog-to-digital converter is designed in the third project. The current-reuse telescopic amplifier with a class-C slew rate booster in the switched-capacitor MDAC was used as the residue amplifier in each stage. Foreground and background calibrations were used to compensate for the inter-stage gain errors, nonlinearities, memory effects, and dynamic non-linearities. The power consumption was 56.0 mW. After digital calibration, the ADC achieved a Schreier’s FoM of 168.4 dB and Walden’s FoM of 24.6fJ/conv at Nyquist frequency.