A High-Speed SAR ADC Achieving High Resolution Using Extra Residue Computation Techniques

Abstract

SAR ADCs aiming to resolve more bits at higher sampling rates suffer from increased DAC area and much more power consumption. A 12 bit SAR ADC is designed which only uses a 10 bit DAC while extra residue computation techniques are utilized to extract 2 extra bits. To counter decreasing feedback loop timing with increasing sampling rates in SAR ADCs, an efficient digital logic is designed to further improve the ADC's speed. A bottom plate sampling technique is utilized to maintain the linearity of the ADC for input frequencies close to Nyquist. For linear sampling, a class AB input buffer followed by bootstrap switches is suggested. The design also uses a low regeneration time comparator coupled with a preamp to reduce kickback. A full transistor-level design of the ADC is proposed for this proposal with special care taken to maintain the linearity of the converter. The ADC achieves a minimum SNDR of 58.4 dB (9.4 ENOB) and SFDR of 76 dB for input frequencies close to Nyquist while operating at 320 MS/s. The ADC core consumes 10.23 mW from a 1.1 V supply and the transistor design is done in TSMC 40nm technology.