dc.contributor.advisor | Sánchez-Sinencio, Edgar | |
dc.creator | Sanabria Borbon, Adriana Carolina | |
dc.date.accessioned | 2021-05-17T15:37:34Z | |
dc.date.available | 2023-05-01T06:36:43Z | |
dc.date.created | 2021-05 | |
dc.date.issued | 2021-03-25 | |
dc.date.submitted | May 2021 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/193118 | |
dc.description.abstract | The continuous technology scaling and rapid growth of applications involving a vast and diverse network of interconnected devices increase analog integrated circuit (IC) design complexity. This work addresses three main trends of analog IC design: highly reconfigurable power-efficient analog circuits, automatic IC design for performance optimization, and analog IP protection against security threats.
The first part of this dissertation discusses the synthesis and design methodology of high-order and frequency-tunable low-pass active-R filter architectures for multi-standard wireless applications. Active-R filters use the inherent integrator-like behavior of amplifiers to realize their frequency response. The main advantages of this type of filter are high-frequency performance and a low integrated area since the only capacitor they require is the Miller capacitor used in internally compensated amplifiers. In this work, amplifiers with configurable unity-gain frequencies enable the continuous tuning of active-R filters. Three different filter architectures realize a fifth-order Butterworth prototype tunable in the 1--50~MHz frequency range.
The second part of this dissertation discusses the development of a computationally low-cost surrogate model for multi-objective optimization-based automated analog IC design. The surrogate has three main components: a set of Gaussian process regression models of the technology's parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs.
Finally, this dissertation presents an overview of analog IP security, including the threat models, protection techniques, and reported attacks. A novel Schmitt-trigger based key provisioning technique is proposed for increasing the security level of existing IP protection techniques. This approach has a very small area overhead that remains constant and independent of the key size. Moreover, it consumes power only at power-up. | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | |
dc.subject | Integrated circuits | en |
dc.subject | analog circuit design | en |
dc.subject | CMOS amplifier | en |
dc.subject | tunable active filters | en |
dc.subject | active-R filter | en |
dc.subject | silicon fabrication | en |
dc.subject | surrogate model | en |
dc.subject | Gaussian process | en |
dc.subject | optimization | en |
dc.subject | hardware security | en |
dc.subject | analog locking | en |
dc.subject | key provisioning. | en |
dc.title | Trends in Analogic Design: Highly Reconfigurable Filters, Performance Optimization and IP Protection | en |
dc.type | Thesis | en |
thesis.degree.department | Electrical and Computer Engineering | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Texas A&M University | en |
thesis.degree.name | Doctor of Philosophy | en |
thesis.degree.level | Doctoral | en |
dc.contributor.committeeMember | Palermo, Samuel | |
dc.contributor.committeeMember | Hu, Jiang | |
dc.contributor.committeeMember | Allaire, Douglas | |
dc.type.material | text | en |
dc.date.updated | 2021-05-17T15:37:35Z | |
local.embargo.terms | 2023-05-01 | |
local.etdauthor.orcid | 0000-0003-3851-6259 | |