200MHz Bandwidth 74DB SNR Continuous Time Delta Sigma ADC for Wireless Application in 40nm CMOS Process

Abstract

This project targets design of a Delta Sigma ADC with a signal bandwidth of 200MHz and an SNR of 74 dB. Reducing the power consumption in the ADC is one of the top priorities during the design phase. To achieve this, in this ADC we implement a summer less feed forward loop filter architecture that reduces the number of opamps in the loop. With this approach we reduced the area and power required for the loop-filter.

One of the issues faced during design of a low OSR high speed Delta Sigma ADC is the stability of the loop with process temperature and voltage (PVT) variations. The variations in opamp bandwidth and gate delays are comparable to clock period. This makes the ADC very sensitive to the process corner. Usually turning the coefficients of the ADC is the approach followed to tackle this issue. This increases production cost since each and every design needs to be tested and trimmed to achieve the performance. Here we implement capacitive DAC based compensation that results in robustness of the NTF across PVT variations inside the chip. This reduced sensitivity if the ADC to process makes it robust towards PVT variations.

ADC performs with 165 dB and a 98 fJ/conv.step FOMsch and FOMW respectively with a quantizer running at 4 GHz speed. The design is implemented in a 40 nm CMOS process. Currently schematic design of the ADC has been done. Layout design for the ADC is on going. Chip is expected to be sent to the foundry in late June 2020.