dc.contributor.advisor | Palermo, Samuel | |
dc.creator | Yang, Hae Woong | |
dc.date.accessioned | 2021-01-12T19:50:07Z | |
dc.date.available | 2021-01-12T19:50:07Z | |
dc.date.created | 2018-12 | |
dc.date.issued | 2018-12-04 | |
dc.date.submitted | December 2018 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/192063 | |
dc.description.abstract | Rapid growing demand for instant multimedia access in a myriad of digital devices has pushed
the need for higher bandwidth in modern communication hardwares ranging from short-reach (SR)
memory/storage interfaces to long-reach (LR) data center Ethernets. At the same time, comprehensive
design optimization of link system that meets the energy-efficiency is required for mobile
computing and low operational cost at datacenters. This doctoral study consists of design of two
low-swing wireline transmitters featuring a low-power clock distribution and 2-tap equalization in
energy-efficient manners up to 20-Gb/s operation. In spite of the reduced signaling power in the
voltage-mode (VM) transmit driver, the presence of the segment selection logic still diminishes the
power saving benefit.
The first work presents a scalable VM transmitter which offers low static power dissipation
and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating
driver segmentation and reducing pre-driver complexity and dynamic power. Per-channel quadrature
clock generation with injection-locked oscillators (ILO) allows the generation of rail-to-rail
quadrature clocks. Energy efficiency is further improved with capacitively driven low-swing global
clock distribution and supply scaling at lower data rates, while output eye quality is maintained at
low voltages with automatic phase calibration of the local ILO-generated quarter-rate clocks. A
prototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock
distribution network and two transmitters that support an output swing range of 100-300mV with
up to 12-dB of equalization. The transmitters achieve 8-16 Gb/s operation at 0.65-1.05 pJ/b energy
efficiency.
The second work involves a dual-mode NRZ/PAM-4 differential low-swing voltage-mode (VM)
transmitter. The pulse-selected output multiplexing allows reduction of power supply and deterministic
jitter caused by large on-chip parasitic inherent in the transmission-gate-based multiplexers
in the earlier work. Analog impedance control replica circuits running in the background produce
gate-biasing voltages that control the peaking ratio for 2-tap feed-forward equalization and
PAM-4 symbol levels for high-linearity. This analog control also allows for efficient generation of
the middle levels in PAM-4 operation with good linearity quantified by level separation mismatch
ratio of 95%. In NRZ mode, 2-tap feedforward equalization is configurable in high-performance
controlled-impedance or energy-efficient impedance-modulated settings to provide performance
scalability. Analytic design consideration on dynamic power, data-rate, mismatch, and output
swing brings optimal performance metric on the given technology node. The proof-of-concept
prototype is verified on silicon with 65 nm CMOS process with improved performance in speed
and energy-efficiency owing to double-stack NMOS transistors in the output stage. The transmitter consumes as low as 29.6mW in 20-Gb/s NRZ and 25.5mW in the 28-Gb/s PAM-4 operations. | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | |
dc.subject | Wireline I/O | en |
dc.subject | PAM-4 | en |
dc.subject | Multi-protocol | en |
dc.subject | ILO | en |
dc.title | Design of Low-Power NRZ/PAM-4 Wireline Transmitters | en |
dc.type | Thesis | en |
thesis.degree.department | Electrical and Computer Engineering | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Texas A&M University | en |
thesis.degree.name | Doctor of Philosophy | en |
thesis.degree.level | Doctoral | en |
dc.contributor.committeeMember | Karsilayan, Aydin | |
dc.contributor.committeeMember | Kish, Laszlo | |
dc.contributor.committeeMember | Mahapatra, Rabi | |
dc.type.material | text | en |
dc.date.updated | 2021-01-12T19:50:08Z | |
local.etdauthor.orcid | 0000-0003-3479-9343 | |