dc.contributor.advisor | Choi, Gwan S | |
dc.creator | Yang, Yoon Seok | |
dc.date.accessioned | 2021-01-11T17:03:14Z | |
dc.date.available | 2021-01-11T17:03:14Z | |
dc.date.created | 2012-08 | |
dc.date.issued | 2012-05-29 | |
dc.date.submitted | August 2012 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/191999 | |
dc.description.abstract | This dissertation presents three design solutions to support several key system-on-chip (SoC) issues to achieve low-power and high performance. These are: 1) joint source and channel decoding (JSCD) schemes for low-power SoCs used in portable multimedia systems, 2) efficient on-chip interconnect architecture for massive multimedia data streaming on multiprocessor SoCs (MPSoCs), and 3) data processing architecture for low-power SoCs in distributed sensor network (DSS) systems and its implementation.
The first part includes a low-power embedded low density parity check code (LDPC) - H.264 joint decoding architecture to lower the baseband energy consumption of a channel decoder using joint source decoding and dynamic voltage and frequency scaling (DVFS). A low-power multiple-input multiple-output (MIMO) and H.264 video joint detector/decoder design that minimizes energy for portable, wireless embedded systems is also designed.
In the second part, a link-level quality of service (QoS) scheme using unequal error protection (UEP) for low-power network-on-chip (NoC) and low latency on-chip network designs for MPSoCs is proposed. This part contains WaveSync, a low-latency focused network-on-chip architecture for globally-asynchronous locally-synchronous (GALS) designs and a simultaneous dual-path routing (SDPR) scheme utilizing path diversity present in typical mesh topology network-on-chips. SDPR is akin to having a higher link width but without the significant hardware overhead associated with simple bus width scaling.
The last part shows data processing unit designs for embedded SoCs. We propose a data processing and control logic design for a new radiation detection sensor system generating data at or above Peta-bits-per-second level. Implementation results show that the intended clock rate is achieved within the power target of less than 200mW. We also present a digital signal processing (DSP) accelerator supporting configurable MAC, FFT, FIR, and 3-D cross product operations for embedded SoCs. It consumes 12.35mW along with 0.167mm2 area at 333MHz. | en |
dc.format.mimetype | application/pdf | |
dc.subject | accelerator | en |
dc.subject | digital signal processing | en |
dc.subject | low-latency | en |
dc.subject | network-on-chip | en |
dc.subject | low-power | en |
dc.subject | system-on-chip | en |
dc.title | Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design | en |
dc.type | Thesis | en |
thesis.degree.department | Electrical and Computer Engineering | en |
thesis.degree.discipline | Computer Engineering | en |
thesis.degree.grantor | Texas A&M University | en |
thesis.degree.name | Doctor of Philosophy | en |
thesis.degree.level | Doctoral | en |
dc.contributor.committeeMember | Gratz, Paul V | |
dc.contributor.committeeMember | Kish, Laszlo B | |
dc.contributor.committeeMember | Sarin, Vivek | |
dc.type.material | text | en |
dc.date.updated | 2021-01-11T17:03:16Z | |