A Design of 12-Bit 125MS/s 3-Bit/Cycle SAR-Based Pipeline ADC Employing a novel amplifier

Abstract

Analog-to-Digital converters (ADCs) are the basic and mandatory building block to link analog to digital world. An amplifier too is key building block for all analog circuit designs. Therefore, this dissertation investigates an ADC design with a novel amplifier design technique. A loop-based gain-boosting technique is presented after reviewing common multi-stage amplifier topologies, miller and feed-forward compensation. Instead of multi-stage amplifier, the proposed technique is still sitting on a single stage amplifier to minimize a power consumption. To achieve high gain as much as a multi-stage amplifier, the proposed design places a loop, which is composed to a Gm-cell and resistors at the output node. The loop at output node helps to boost output impedance resulting in the increase of DC gain and the push of the 1st pole to lower frequency while maintaining the same gain-bandwidth product (GBW). Even though the loop also adds a parasitic pole into the entire amplifier response, a zero formed by a feed-forward path of the loop is placed at the exactly same position of the parasitic pole. Moreover, since the parasitic pole is located at out-of-band, it helps to keep the phase margin more than 60 degree. The prototype is fabricated with TSMC 40-nm technology. It achieves the gain of 35.9 dB and more than 80 degree of phase margin with power consumption of 1.6 mW in 1.3 V power supply. The overall performance of proposed amplifier is IFoM1 of 650 MHzpF/mA and FoM1 of 500 MHzpF/mA. This dissertation introduces a 12 bit 2.5 bit/cycle SAR-based pipeline ADC employing a self-bias gain boosting amplifier. The single-stage amplifier achieves a low-frequency gain of 37 dB, while consuming 1.3 mW of power consumption with 1.3 V of analog power supply. A 2.5 bit/cycle SAR ADC realizes as the sub-ADC in each stage, and reduces both power consumption and silicon area. A two-channel sampling architecture is employed to double the sampling rate and thereby maximizes circuit efficiency. A digital calibration technique is used to reduce non-linearity and mismatches due to the RDAC, as well as gain error and offset of the residue amplifier. The prototype ADC was fabricated in TSMC 40-nm technology, and consumes 10.71 mW with 1.1 V / 1.3 V digital / analog power supplies. When operating at 125 MS/s, the ADC achieves an SFDR of 66.59 dB before calibration and 80.3 dB after calibration when measured at Nyquist frequency. The architecture shows a Walden FoM of 101 fJ/c.-s. before calibration and 47 fJ/c.-s. after calibration.