Show simple item record

dc.contributor.advisorHu, Jiang
dc.contributor.advisorTyagi, Aakash
dc.creatorJagadeesh, Amrutha Shikaripura
dc.date.accessioned2020-03-10T19:19:55Z
dc.date.available2020-03-10T19:19:55Z
dc.date.created2019-05
dc.date.issued2019-04-05
dc.date.submittedMay 2019
dc.identifier.urihttps://hdl.handle.net/1969.1/187544
dc.description.abstractFunctional verification is used to confirm that the logic of a design meets its specification. The most commonly used method for verifying complex designs is simulation-based verification. The quality of simulation-based verification is based on the quality and diversity of the tests that are simulated. However, it is time consuming and compute intensive on account of the fact that a large volume of tests must be simulated to exhaustively exercise the design functionality in order to find and fix logic bugs. A common measure of success of this exercise is in the form of a metric known as functional coverage. Coverage is typically indicated as a percentage of functionality covered by the test suite. This thesis proposes a novel methodology to construct a model using SVM, Gradient Boosting Classifier and Neural Networks aimed at replacing random test generation for speeding up coverage collection.en
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectFunctional Verificationen
dc.subjectCoverageen
dc.subjectRandom Test Generation.en
dc.titleAccelerating Coverage Closure For Hardware Verification Using Machine Learningen
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberHou, I-Hong
dc.type.materialtexten
dc.date.updated2020-03-10T19:19:55Z
local.etdauthor.orcid0000-0003-3465-9068


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record