Jitter Tolerant Hybrid Sigma-Delta Modulator

Abstract

Commonly used in wireless applications and consumer products, Continuous-time (CT) Sigma Delta (Σ∆) Analog to Digital Converter (ADC) stands out for its high resolution, less input signal conditioning and large incorporating with digital signal processing. The clock jitter impact on CT Σ∆ ADC is a critical issue as it will directly increase the noise floor within signal bandwidth. Thus, reducing jitter sensitivity is beneficial for improving the performance of CT Σ∆ ADC. This thesis presents a novel idea of reducing CT Σ∆ ADC jitter sensitivity by splitting one stage of continuous-time integrator into two parts - a gain stage and a digital low-pass filter. The gain stage remains prior to quantizer for compensating the loss of loop gain when removing the original continuous-time integrator. The digital filter is placed at the output of quantizer to suppress the out-of-band noise level. This hybrid Σ∆ ADC is implemented with two configurations in system level with TSMC 40nm CMOS technology at 20 MHz bandwidth and 640 MHz sampling frequency. The maximum SNR of the hybrid Σ∆ ADC is 69.18 dB. The proposed ADC achieves the maximum of 14 dB better SQNR than the conventional CT Σ∆ ADC at RMS jitter as high as 10% of the clock period. A negative resistor gain boosting single stage amplifier is also presented in this thesis.