dc.contributor.advisor | Silva-Martinez, Jose | |
dc.creator | Guan, Li | |
dc.date.accessioned | 2019-11-20T23:07:07Z | |
dc.date.available | 2019-11-20T23:07:07Z | |
dc.date.created | 2019-08 | |
dc.date.issued | 2019-07-16 | |
dc.date.submitted | August 2019 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/186255 | |
dc.description.abstract | This thesis introduces a gain-compensated external capacitor-less low-dropout voltage regulator with total 5.7 uA quiescent current at all load conditions. The two-stage gain-compensated error amplifier is implemented with a cross-couple pair negative resistor to make the LDO achieve higher gain (> 50 dB) with very low bias current (< 1.3 uA). The LDO can achieve 52 dB loop gain at no load condition, 64 dB at 1 mA and 54 dB at 100 mA load.
During transients (0 A to 100 mA) the undershoot is optimized to 98.6 mV with 100 ns rising and falling time through a differentiator circuit to boost the LDO’s transient response. The phase margin of the proposed LDO is 55◦ at 1 mA and 79.27◦ at max load (100 mA). Figure of merit (FOM) of this work is 2.79 fs which is very small. | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | |
dc.subject | LDO | en |
dc.subject | Gain-compensated | en |
dc.subject | Capacitor-less | en |
dc.title | Design of a Low Power External Capacitor-Less Low-Dropout Regulator with Gain-Compensated Error Amplifier | en |
dc.type | Thesis | en |
thesis.degree.department | Electrical and Computer Engineering | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Texas A&M University | en |
thesis.degree.name | Master of Science | en |
thesis.degree.level | Masters | en |
dc.contributor.committeeMember | Karsilayan, Aydin | |
dc.contributor.committeeMember | Bhattacharyya, Shankar | |
dc.contributor.committeeMember | Kim, Won-Jong | |
dc.type.material | text | en |
dc.date.updated | 2019-11-20T23:07:08Z | |
local.etdauthor.orcid | 0000-0002-9616-9876 | |