Show simple item record

dc.contributor.advisorHu, Jiang
dc.contributor.advisorHuang, Jeff
dc.creatorRachala, Abhijith Reddy
dc.date.accessioned2019-11-20T23:05:34Z
dc.date.available2019-11-20T23:05:34Z
dc.date.created2019-08
dc.date.issued2019-07-11
dc.date.submittedAugust 2019
dc.identifier.urihttps://hdl.handle.net/1969.1/186252
dc.description.abstractComputer security is a very critical problem these days, as it has widespread consequences in case of a failure of computer systems security, like desktop machines, mobile phones, tablets and Internet of Things (IoT) devices. Usually, attackers try to find vulnerabilities in the target systems and by exploiting these vulnerabilities, they launch an attack, thereby achieving their malicious goal. Software data attacks modify the intended control/data flow in a program that is unprotected. Control data attacks are executed by exploiting buffer overflows or string vulnerabilities to overwrite a return address, a function pointer or some other information about control data. Non-control data attacks exploit similar vulnerabilities to overwrite security critical data without changing the intended control-flow in the program. Data flow integrity ensures that the flow of data in a program at runtime is permitted by the data flow graph. The main objective of the thesis is to implement a hardware-based data flow integrity technique and check for vulnerabilities on a target application. This implementation is achieved by referencing a data flow graph against which the runtime data flow of a program is checked. DFI checking is integrated into existing processor with most changes in hardware going to the load/store unit and the arithmetic unit. In gem5, this is realised by modifying source code of the simulator at instruction level to monitor each load/store instruction on the target application and check if there are any data flow violations and check the overhead caused by the modification of gem5 source code to integrate DFI checking with existing CPU models on gem5. From experiments results, we measured the performance overhead to be up to 14.5%. We also roughly estimate the extra hardware required for this implementation on real hardware.en
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectData Flow Integrityen
dc.subjectgem5en
dc.subjectSecurityen
dc.subjectComputer architectureen
dc.titleEvaluation of Hardware-based Data Flow Integrityen
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberAnnapareddy, Narasimha
dc.type.materialtexten
dc.date.updated2019-11-20T23:05:34Z
local.etdauthor.orcid0000-0001-5995-5205


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record