Energy Efficient Wireless Circuits for IoT in CMOS Technology

Abstract

The demand for efficient and reliable wireless communication equipment is increasing at a rapid pace. The demand and need vary between different technologies including 5G and IoT. The Radio Frequency Integrated Circuits (RFIC) designers face challenges to achieve higher performance with lower power resources. Although advances in Complementary Metal-Oxide-Semiconductor (CMOS) technology has help designers, challenges still exist. Thus, novel and new ideas are welcome in RFIC design. In this dissertation, many ideas are introduced to improve efficiency and linearity for wireless receivers dedicated to IoT applications. A low-power wireless RF receiver for wireless sensor networks (WSN) is introduced. The receiver has improved linearity with incorporated current-mode circuits and high-selectivity filtering. The receiver operates at a 900 MHz industrial, scientific and medical (ISM) band and is implemented in 130 nm CMOS technology. The receiver has a frequency multiplication mixer, which uses a 300 MHz clock from a local oscillator (LO). The local oscillator is implemented using vertical delay cells to reduce power consumption. The receiver conversion gain is 40 dB and the receiver noise figure (NF) is 14 dB. The receiver IIP3 is −6 dBm and the total power consumption is 1.16 mW. A wireless RF receiver system suitable for Internet-of-Things (IoT) applications is presented. The system can simultaneously harvest energy from out-of-band (OB) blockers with normal receiver operation; thus, the battery life for IoT applications can be extended. The system has only a single antenna for simultaneous RF energy harvesting and wireless reception. The receiver is a mixer-first quadrature receiver designed to tolerate large unavoidable blockers. The system is implemented in 180 nm CMOS technology and operates at 900 MHz industrial, scientific and medical (ISM) band. The receiver gain is 41.5 dB. Operating from a 1 V supply, the receiver core consumes 430 µW. This power can be reduced to 220 µW in the presence of a large blocker (≈ 0 dBm) by the power provided by the blocker RF energy harvesting where the power conversion efficiency (PCE) is 30%. Finally, a highly linear energy efficient wireless receiver is introduced. The receiver architecture is a mixer-first receiver with a Voltage Controlled Oscillator (VCO) based amplifier incorporated as baseband amplifier. The receiver benefits from the high linearity of this amplifier. Moreover, novel clock recycling techniques are applied to make use of the amplifier’s VCOs to clock the mixer circuit and to improve power consumption. The system is implemented in 130 nm CMOS technology and operates at 900 MHz ISM band. The receiver conversion gain is 42 dB and the power consumption is 2.9 mW. The out-of-band IIP3 is 6 dBm. All presented systems and circuits in this dissertation are validated and published in various IEEE journals and conferences.