Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip
Abstract
Scalable Networks-on-Chip (NoCs) have become the de facto interconnection mechanism in
large scale Chip Multiprocessors. NoCs devour a large fraction of the on-chip power budget of
which static NoC power consumption is becoming the dominant component as technology scales
down. Hence, reducing static NoC power consumption is critical for energy-efficient computing.
Previous research suggests power-gating routers attached to inactive cores so as to save static
power, but requires centralized control and global network knowledge. Moreover, packet deliveries
in irregular power-gated network suffer from detour or waiting time overhead to either route around
or wake up off routers. Fly-Over (FLOV) is a distributed power-gating mechanism to minimize
static power consumption in NoCs without the need for global network information. However, the
existing FLOV routing algorithm introduces unnecessary detours and pressurizes the routers in
AON column resulting in high packet latencies and network congestion.
This work proposes FLOV+, Best-Effort Minimal Routing Algorithm for Fly-Over (FLOV) to
route the packets using the shortest path in an irregular power-gated network and also relieve the
stress on the AON column. This routing algorithm aims to minimize the average packet latency and
to sustain throughput in network with power-gated routers. Synthetic workload evaluations show
that the proposed algorithm reduces average packet latency upto 9.84% in an 8-dimensional mesh
network. Simulation results also show 50% and 40% improvement in the network throughput for
restricted FLOV and generalized FLOV power gating mechanisms respectively.
Citation
Bhosekar, Shilpa (2018). Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip. Master's thesis, Texas A & M University. Available electronically from https : / /hdl .handle .net /1969 .1 /174084.