| dc.description.abstract | The ubiquitous presence of wireless and battery-powered devices is an inseparable and invincible feature of our modern life. Meanwhile, the spectrum aggregation, and limited battery capacity of handheld devices challenge the exploding demand and growth of such radio systems. In this work, we try to present two separate solutions for each case; an ultra-wideband (UWB) receiver for Cognitive Radio (CR) applications to deal with spectrum aggregation, and an ultra-low power (ULP) receiver to enhance battery life of handheld wireless devices.
Limited linearity and LO harmonics mixing are two major issues that ultra-wideband receivers, and CR in particular, are dealing with. Direct conversion schemes, based on current-driven passive mixers, have shown to improve the linearity, but unable to resolve LO harmonic mixing problem. They are usually limited to 3rd, and 5th harmonics rejection or require very complex and power hungry circuitry for higher number of harmonics. This work presents a heterodyne up-down conversion scheme in 180 nm CMOS technology for CR applications (54-862 MHz band) that mitigates the harmonic mixing issue for all the harmonics, while by employing an active feedback loop, a comparable to the state-of-the art IIP3 of better than +10 dBm is achieved. Measurements show an average NF of 7.5 dB when the active feedback loop is off (i.e. in the absence of destructive interference), and 15.5 dB when the feedback loop is active and a 0 dBm interferer is applied, respectively.
Also, the second part of this work presents an ultra-low power super-regenerative receiver (SRR) suitable for OOK modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40 nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through Successive Approximation Register (SAR) architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single-ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 µW from a 0.65 V supply results in an excellent energy efficiency of 80 pJ/b at 4 Mb/s data rate. The receiver also employs an ADC that enables soft-decisioning and a convenient sensitivity-data rate trade-off, achieving sensitivity of -86.5, and -101.5 dBm at 1000 and 31.25 kbps data rate, respectively | en |
