| dc.description.abstract | Nowadays, the rapid development of system-on-chip (SoC) market introduces
tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC
fabrication process is scaling down to allow higher density of integration but makes
the chips more sensitive to the process-voltage-temperature (PVT) variations. A
successful IC product not only imposes great pressure on the IC designers, who have
to handle wider variations and enforce more design margins, but also challenges the
test procedure, leading to more check points and longer test time. To relax the
designers’ burden and reduce the cost of testing, it is valuable to make the IC chips
able to test and tune itself to some extent.
In this dissertation, a fully integrated in-situ design validation and optimization
(VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test
(BIST) techniques for analog circuits. Based on the data collected from BIST,
the error between the measured and the desired performance of the target circuit is
evaluated using a cost function. A digital multi-dimensional optimization engine is
implemented to adaptively adjust the analog circuit parameters, seeking the minimum
value of the cost function and achieving the desired performance. To verify
this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd
order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip.
Apart from the VO system, several improved BIST techniques are also proposed
in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to
enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of
59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion
current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to
two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration.
Moreover, an on-chip RF receiver linearity BIST methodology for continuous and
discrete-time hybrid baseband chain is proposed. The proposed receiver chain
implements a charge-domain FIR filter to notch the two excitation signals but expose
the third order intermodulation (IM3) tones. It simplifies the linearity measurement
procedure–using a power detector is enough to analyze the receiver’s linearity.
Finally, a low cost fully digital built-in analog tester for linear-time-invariant
(LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to
measure the delays corresponded to a ramp excitation signal and is able to estimate
the pole or zero locations of a low-pass LTI system. | en |
