dc.contributor.advisor | Entesari, Kamran | |
dc.creator | Attah, Hubert | |
dc.date.accessioned | 2016-07-08T15:08:28Z | |
dc.date.available | 2018-05-01T05:48:40Z | |
dc.date.created | 2016-05 | |
dc.date.issued | 2016-02-02 | |
dc.date.submitted | May 2016 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/156859 | |
dc.description.abstract | Frequency synthesizers have become a crucial building block in the evolution of modern communication systems and consumer electronics. The spectral purity performance of frequency synthesizers limits the achievable data-rate and presents a noise-power tradeoff. For communication standards such as LTE where the channel spacing is a few kHz, the synthesizers must provide high frequencies with sufficiently wide frequency tuning range and fine frequency resolutions. Such stringent performance must be met with a limited power and small chip area.
In this thesis a wideband fractional-N frequency synthesizer based on a subsampling phase locked loop (SSPLL) is presented. The proposed synthesizer which has a frequency resolution less than 100Hz employs a digital fractional controller (DFC) and a 10-bit digital-to-time converter (DTC) to delay the rising edges of the reference clock to achieve fractional phase lock. For fast convergence of the delay calibration, a novel two-step delay correlation loop (DCL) is employed. Furthermore, to provide optimum settling and jitter performance, the loop transfer characteristics during frequency acquisition and phase-lock are decoupled using a dual input loop filter (DILF).
The fractional-N sub-sampling PLL (FNSSPLL) is implemented in a TSMC 40nm CMOS technology and occupies a total active area of 0.41mm^2. The PLL operates over frequency range of 2.8 GHz to 4.3 GHz (42% tuning range) while consuming 9.18mW from a 1.1V supply. The integrated jitter performance is better than 390 fs across all fractional frequency channel. The worst case fractional spur of -48.3 dBc occurs at a 650 kHz offset for a 3.75GHz fractional channel. The in-band phase noise measured at a 200 kHz offset is -112.5 dBc/Hz. | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | |
dc.subject | CMOS RF | en |
dc.subject | PLL | en |
dc.subject | Wideband | en |
dc.subject | Fractional-N PLL | en |
dc.subject | SSPLL | en |
dc.subject | DTC | en |
dc.subject | DCL | en |
dc.subject | DILF | en |
dc.title | A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL) | en |
dc.type | Thesis | en |
thesis.degree.department | Electrical and Computer Engineering | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Texas A & M University | en |
thesis.degree.name | Master of Science | en |
thesis.degree.level | Masters | en |
dc.contributor.committeeMember | Palermo, Samuel | |
dc.contributor.committeeMember | Zou, Jun | |
dc.contributor.committeeMember | Zoghi, Behbood | |
dc.type.material | text | en |
dc.date.updated | 2016-07-08T15:08:28Z | |
local.embargo.terms | 2018-05-01 | |
local.etdauthor.orcid | 0000-0003-2205-7086 | |