dc.contributor.advisor | Palermo, Samuel | |
dc.creator | Song, Younghoon | |
dc.date.accessioned | 2015-01-09T19:57:15Z | |
dc.date.available | 2016-05-01T05:30:52Z | |
dc.date.created | 2014-05 | |
dc.date.issued | 2014-01-02 | |
dc.date.submitted | May 2014 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/152468 | |
dc.description.abstract | Total I/O bandwidth demand is growing in high-performance systems due to the emergence of many-core microprocessors and in mobile devices to support the next generation of multi-media features. High-speed serial I/O energy efficiency must improve in order to enable continued scaling of these parallel computing platforms in applications ranging from data centers to smart mobile devices.
The first work, a low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100-200 mV_(ppd) using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range.
Low-power high-speed serial I/O transmitters which include equalization to compensate for channel frequency dependent loss are required to meet the aggressive link energy efficiency targets of future systems. The second work presents a low power serial link transmitter design that utilizes an output stage which combines a voltage-mode driver, which offers low static-power dissipation, and current-mode equalization, which offers low complexity and dynamic-power dissipation. The utilization of current-mode equalization decouples the equalization settings and termination impedance, allowing for a significant reduction in pre-driver complexity relative to segmented voltage-mode drivers. Proper transmitter series termination is set with an impedance control loop which adjusts the on-resistance of the output transistors in the driver voltage-mode portion. Further reductions in dynamic power dissipation are achieved through scaling the serializer and local clock distribution supply with data rate.
Finally, it presents that a scalable quarter-rate transmitter employs an analog-controlled impedance-modulated 2-tap voltage-mode equalizer and achieves fast power-state transitioning with a replica-biased regulator and ILO clock generation. Capacitively-driven 2 mm global clock distribution and automatic phase calibration allows for aggressive supply scaling. | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | |
dc.subject | High speed I/O | en |
dc.subject | energy efficient I/O | en |
dc.title | Design Techniques for Energy Efficient Multi-GB/S Serial I/O Transceivers | en |
dc.type | Thesis | en |
thesis.degree.department | Electrical and Computer Engineering | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Texas A & M University | en |
thesis.degree.name | Doctor of Philosophy | en |
thesis.degree.level | Doctoral | en |
dc.contributor.committeeMember | Sanchez-Sinencio, Edgar | |
dc.contributor.committeeMember | Chang, Kai | |
dc.contributor.committeeMember | Walker, Duncan M | |
dc.type.material | text | en |
dc.date.updated | 2015-01-09T19:57:15Z | |
local.embargo.terms | 2016-05-01 | |