Browsing by Subject "buffer insertion"
Now showing items 1-4 of 4
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(2012-10-19)In this thesis, we proposed an intermediate sub-process between placement and routing stage in physical design. The algorithm is for generating layer guidance for post-placement optimization technique especially buffer ...
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(2015-08-11)VLSI technology scaling has caused interconnect delay to increasingly dominate the overall chip performance. Optimization techniques such as buffer insertion, wire sizing and layer assignment play critical roles in successful ...
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(2009-05-15)As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic ...
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(2013-08-01)With the advances in process technology, comes the domination of interconnect in the overall propagation delay in modern VLSI designs. Hence, interconnect synthesis techniques, such as buffer insertion, wire sizing and ...