Browsing by Subject "STT-MRAM"

Now showing items 1-3 of 3

    • A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects 
      Kansal, Rohan (2013-08-09)
      Network-on-Chip (NoC) is a de facto inter-core communication infrastructure for future Chip Multiprocessors (CMPs). NoC should be designed to provide both low latency and high bandwidth considering limited on-chip power ...
    • STT-MRAM Based NoC Buffer Design 
      Vikram Kulkarni, Nikhil (2012-10-19)
      As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory - STT MRAM (Spin-Torque Transfer ...
    • Throughput-Efficient Network-on-Chip Router Design with STT-MRAM 
      Narayana, Sagar 1986- (2012-11-02)
      As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck ...