Browsing by Subject "H03M 13/1128"

Now showing items 1-9 of 9

    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2018-11-27)
      A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2018-11-27)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2021-03-16)
      A method and system for decoding low density parity check ("LDPC") codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2020-04-07)
      A method and system for decoding low density parity check ("LDPC") codes. A method and system for decoding low density parity check ("LDPC") codes. An LDPC code decoder includes decoding circuitry configured to process ...
    • Low Density Parity Check Decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 6/21/2022)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an ...
    • Low density parity check decoder for irregular LDPC codes 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2013-10-08)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density ...
    • Low density parity check decoder for irregular LDPC codes 
      Gunnam, Kiran K.; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2013-04-09)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density ...
    • Low density parity check decoder for regular LDPC codes 
      Gunnam, Kiran K.; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2013-01-22)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R ...
    • Low density parity check decoder for regular LDPC codes 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2014-02-18)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R ...