Browsing by Subject "Crosstalk"

Now showing items 1-5 of 5

    • Communication Reliability in Network on Chip Designs 
      Kumar, Reeshav (2012-10-19)
      The performance of low latency Network on Chip (NoC) architectures, which incorporate fast bypass paths to reduce communication latency, is limited by crosstalk induced skewing of signal transitions on link wires. As a ...
    • MACHINE-LEARNING TECHNIQUES FOR VLSI DESIGN AUTOMATION 
      Liang, Rongjian (2021-12-02)
      VLSI design productivity has already become the bottleneck to take full advantage of potential benefit brought by technology scaling, leading to the famous design productivity gap, i.e., the mismatch between the available ...
    • Maximizing Crosstalk-Induced Slowdown During Path Delay Test 
      Gope, Dibakar (2012-10-19)
      Capacitive crosstalk between adjacent signal wires in integrated circuits may lead to noise or a speedup or slowdown in signal transitions. These in turn may lead to circuit failure or reduced operating speed. This thesis ...
    • Statistical static timing analysis considering process variations and crosstalk 
      Veluswami, Senthilkumar (Texas A&M University, 2005-11-01)
      Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die variations have ...
    • Track Assignment Considering Crosstalk-Induced Performance Degradation 
      Zhao, Qiong (2012-07-16)
      Track assignment is a critical step between global routing and detailed routing in modern VLSI chip designs. It greatly affects some very important design characteristics, such as routability, via usage and timing performance. ...