Browsing by Author "Selvarathinam, Anand Manivannan"

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    • Generation of RTL verification input stimulus 
      Selvarathinam, Anand Manivannan (Texas A&M University, 2001)
      This thesis presents an approach for generating input stimulus for verification of register-transfer level (RTL) design of VLSI circuits. RTL design is often subjected to a significant verification effort due to errors ...
    • High throughput low power decoder architectures for low density parity check codes 
      Selvarathinam, Anand Manivannan (Texas A&M University, 2005-11-01)
      A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design ...