Design of a Wide Bandwidth Continuous-time Low-pass Sigma-delta Modulator
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The emergence of bandwidth-intensive services has created a need for high speed and high resolution data converters. Towards this end, system level design of a continuous-time sigma-delta modulator achieving 11 bits resolution over 100 MHz signal bandwidth by using a feed-forward topology is presented. The system is first built in the Simulink environment in MATLAB. The building blocks in the loop filter are modeled with non-idealities, and specifications for these blocks are obtained by simulations. An operational transconductor amplifier (OTA) with 100 mS transconductance, 70 dB linearity, and 34.2 mW power dissipation is designed to be used in the loop filter. Simulation results indicate that the 5th order loop filter implemented in the feed-forward architecture in transistor level shows lower power consumption, 105 mW, compared to the loop filter implemented by feedback architecture, 152 mW.
Chien, Cheng-Ming (2011). Design of a Wide Bandwidth Continuous-time Low-pass Sigma-delta Modulator. Master's thesis, Texas A&M University. Available electronically from