| dc.description.abstract | Technology scaling has been the most obvious choice of designers and chip
manufacturing companies to improve the performance of analog and digital circuits.
With the ever shrinking technological node, process variations can no longer be ignored
and play a significant role in determining the performance of nanoscaled devices. By
choosing a worst case design methodology, circuit designers have been very munificent
with the design parameters chosen, often manifesting in pessimistic designs with
significant area overheads.
Significant work has been done in estimating the impact of intra-die process
variations on circuit performance, pertinently, noise margin and standby leakage power,
for fixed transistor channel dimensions. However, for an optimal, high yield, SRAM cell
design, it is absolutely imperative to analyze the impact of process variations at every
design point, especially, since the distribution of process variations is a statistically
varying parameter and has an inverse correlation with the area of the MOS transistor.
Furthermore, the first order analytical models used for optimization of SRAM memories
are not as accurate and the impact of voltage and its inclusion as an input, along with
other design parameters, is often ignored.
In this thesis, the performance parameters of a nano-scaled 6-T SRAM cell are
modeled as an accurate, yield aware, empirical polynomial predictor, in the presence of
intra-die process variations. The estimated empirical models are used in a constrained
non-linear, robust optimization framework to design an SRAM cell, for a 45 nm CMOS
technology, having optimal performance, according to bounds specified for the circuit
performance parameters, with the objective of minimizing on-chip area. This statistically aware technique provides a more realistic design methodology to study the trade off
between performance parameters of the SRAM.
Furthermore, a dual optimization approach is followed by considering SRAM
power supply and wordline voltages as additional input parameters, to simultaneously
tune the design parameters, ensuring a high yield and considerable area reduction. In
addition, the cell level optimization framework is extended to the system level
optimization of caches, under both cell level and system level performance constraints. | en |
