A methodology for memory chip stress levels prediction
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The reliability of electronic component plays an important role in proper functioning of the electronic devices. The manufacturer tests electronic components before they are used by end users. Still at times electronic devices fail due to undue stresses existing inside the microelectronic components such as memory chips, microcontrollers, resistors etc. The stresses can be caused by variation in the operating voltage, variation in the usage frequency of the particular chip and other factors. This variation leads to variation in chip temperature, which can be made evident from thermal profiles of these chips. In this thesis, effort was made to study two different kind of stress existing in the electronic board, namely signal stress based on variation in duty cycle/frequency of chip usage and the voltage stress. Memory chips were stressed using these stresses causing change in heating rates, which were captured by infrared camera. This data was then extracted and plotted to obtain different curves for the heating rate. The same experiment was done time and again for a large number of chips to get heating rate data. This data consisting of average heating rate for large number of chips was used to build Neural Network model (NN). Back Propagation algorithm was used for modeling because of its advantage of converging to solution faster compared to other algorithms. To develop a prediction model, data sets were divided into two-third and one-third parts. This two-thirds of the data was used to build the prediction model and remaining one third was used to evaluate the model. The designed model would predict the stress levels existing in the chips based on the heating rates of the chips. Results obtained suggested 1. There is difference in heating rate for chips stressed at different stress levels. 2. Accuracy of the model to predict the stress is high (greater than 90 %). 3. Model is robust enough that is it can yield efficient results even if there is presence of noise in the data. 4. Generic methodology can be proposed based on the experiments. This work is a progress in direction of making predictive model, for a complete electronic device, which can predict the stress level existing on any component in the device and will provide an opportunity to either protect the data or removal of the defected components timely before it even fails.
Sharma, Kartik (2005). A methodology for memory chip stress levels prediction. Master's thesis, Texas A&M University. Texas A&M University. Available electronically from