| dc.description.abstract | The explosion in network traffic driven by cloud computing and wireless data usage necessitates serial I/O operate at higher data rates. The per-channel I/O data rate is projected over 100Gb/s due to packaging technology allowing only modest increases in I/O channel number. As the high-speed data symbol times shrink, this results in an increased amount of inter symbol interference (ISI) for transmission over both severe low-pass electrical channels and dispersive optical channels. This necessitates increased equalization complexity, consideration of more bandwidth-efficient modulation schemes, such as baseband PAM4 and coherent QAM, and the use of forward error correction. Serial links that utilize an analog-to-digital converter (ADC) receiver front-end offer a potential solution, as they enable more powerful and flexible digital signal processing (DSP) for equalization and symbol detection and can easily support advanced modulation schemes. Moreover, the DSP back-end provides robustness to process, voltage, and temperature variations, and benefits from improved area and power with CMOS technology scaling. However, with the data-rate increasing to 100+ GS/s, the front-end ADC for PAM 4 modulation requires 50G+ GS/s sample rate, and high input bandwidth is essential for less induced ISI. Power consumption of such high-speed ADC is a major problem. This motivates the exploration of energy-efficient high-speed and high-bandwidth time-interleaved ADC design. In addition to this, sampling clock jitter places fundamental performance limitations on common time-interleaved ADC architectures, necessitating clock generation and distribution circuitry that achieve rms jitter of a few hundred of femtoseconds.
This dissertation presents three researches. The first work presents a 1.5GS/s 8-bit unit pipeline-SAR ADC on 14nm with output level shifting techniques that significantly reduce the unit-ADC power and maintain the high-speed. The unit-ADC operates with a 0.8V supply, consumes 2.4mW power, and achieves16.7fJ/conv.-step FOM at Nyquist. The second research presents a high-speed time-interleaved ADC, proposed a speed-enhanced bootstrapped switch that enable a low-power and high bandwidth interleaver. A 7-bit 38GS/s ADC 22nm prototype achieves 41.9fj/conv.-step at low frequency, 64.1fj/conv.-step at Nyquist, and has a 20GHz 3dB bandwidth. The third research is a novel frequency domain multi-carrier ADC-based receiver front-end. The multi-carrier technique significantly improves jitter robustness and reduce the conversion speed of front-end ADC as well as the DSP complexity. A 40Gb/s receiver frontend 22nm prototype can operate with the highest 1.6psrms jitter and achieves 3.05pJ/bit power efficiency. | |
