Simulation of Address Translation Techniques
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As the memory footprints of modern compute workloads continue to grow, pressure on the memory hierarchy increases and address translations play an increasingly important role in system performance. Translation Lookaside Buffers (TLB) are a vital structure to the performance of modern virtual memory systems. They reduce the need for slow and expensive page walks by caching the most recent virtual-to-physical address translations. We analyze how well the cost of the page walk can be approximated in a five level memory hierarchy, and how simple and hypothetical optimizations are able to affect the memory system performance. Initially we compare the performance of a realistic page walker to a fixed page walk penalty. This allows for future work to presume a demonstrably reasonable constant value in experimenta- tion, not relying on intuition and saving on the additional time and energy of a simulated page walk. A suggested fixed value is put forward as well as an analysis of the variability across workloads and any limitations. Making use of this fixed page walk penalty, we also look at the effect of a simple TLB op- timization - doubling the available resources. allows us to asses the affect of the TLB on the memory system performance and discuss both what a future optimization may look like and what performance can be both reasonably expected and hoped for. We analyze one potential in-TLB optimization, CHiRP, which seeks a replacement policy for the TLB more appropriate and optimized for the structure than least-recently-used (LRU). We analyze the structure of the policy and also the results of the CHiRP work against our hypothetical performance improvements. A strategy related to prefetching is also analyzed. ASAP which prefetches inside of and relevant only to a particular page walk is examined.
Coman, James (2021). Simulation of Address Translation Techniques. Master's thesis, Texas A&M University. Available electronically from