High Linearity Techniques for Analog Filters, Built-in Testing and Impedance Spectroscopy in Scaled CMOS Technologies
Abstract
With the advances in CMOS technology, the minimum feature sizes and the threshold voltage of the transistors are continuing to scale down. This scaling down allows an increasing count of transistors per unit area, increasing device speed, and lowering power consumption. This technological trend has fueled enormous advancement in the development of low-cost and feature-rich system-on-chip (SoC) products. Today’s SoCs often integrate a complete electronic system in a single CMOS platform, including highly-complex digital circuits, high-fidelity analog peripherals, radio-frequency (RF) circuits, and power management circuits. Advancement in SoC enabled new technologies such as smart homes, smart cities, and wearable medical devices. However, the increasing number of integrated analog parts that coexist with digital circuits brings several challenges, such as the aggressive reduction in supply voltage and increased susceptibility to the process, voltage, and temperature (PVT) variations. These challenges motivated exploring alternative forms of analog signal representation, such as the time/phase domain and created new topologies of analog circuits that take advantage of CMOS technology scaling. Moreover, analog built-in-self-test (BIST) is becoming inevitable with the increased number of analog components per integrated circuit (IC) and increased intra-die and inter-die process variability. Furthermore, SoC technologies have enabled advancement in hand-held medical devices, which is becoming an essential driver for the future consumer electronics market. In this dissertation, challenges and solutions for these research topics are explored.
First, a new class of phase-mode ring oscillator (RO)-based filters that address linearity and process variance limitation of existing RO-based filters is presented. A highly-linear process-tolerant RO filter topology is achieved by imitating the widely known active-RC topology in the phase domain. We propose utilizing a set of frequency detectors (FDs) and phase detectors (PDs) to extract both the frequency and phase information of an inverter-based RO to synthesize active filters in a way similar to integrator-based active-RC filters, which are synthesized using a set of capacitors and resistors, respectively. A zero-compensation technique is proposed to extend the achievable bandwidth of the proposed topology. Also, a delay-locked loop (DLL)-based tuning scheme is introduced to achieve resilience over PVT variations. A prototype 5th-order, 2–22 MHz continuous-time Butter- worth filter is presented in 130 nm CMOS technology to demonstrate the proposed topology. The filter consumes 6.2–8.9 mA from a 1 V supply and achieves 26.2 dB in-band IIP3. The filter achieves bandwidth variation less than ±3.5% over a temperature range of -40 °C to 85 °C and supply voltage range of 0.9–1.2 V.
Second, a harmonic-canceling sinewave generator for analog BIST applications. An architectural solution to implement the irrational coefficient of the sampled half-sine harmonic- canceling filter (HCF) is presented. The proposed technique relaxes the trade-off between output linearity and coefficients mismatch. The cascade of HCFs allows to filter out up to the 47th harmonic of an input square-wave. Additionally, the system is fully reconfigurable to implement different order HCFs and can be configured to enhance either the fundamental harmonic or the 5th harmonic of an input square wave, which extends the output frequency range. The system is fabricated in 180nm CMOS technology. Measurement results show a maximum of 66 dBc spurious-free dynamic range (SFDR) and output frequencies ranging from 0.8 MHz to 100 MHz.
Finally, an impedance analyzer with an on-chip stimulus generator (SG) for bioimpedance spectroscopy applications is presented. The system provides sub-GΩ impedance measurement with less than 1.2% error over the frequency range of 0.01–100 kHz. The impedance analyzer system prototype is implemented in 180-nm CMOS technology, the SG and the impedance read-out (IRO) circuits consume 0.64 mW and 0.32 mW respectively from a 1.8V supply.
Subject
Analog filtercontinuous time filter
low voltage filters
ring oscillator filters
phase domain signal processing
analog built-in testing
harmonic cancellation
single tone synthesizer
impedance analyzer
bio-impedance
impedance spectroscopy
Citation
Osman, Hatem Mahmoud Abdelkhalek Mohamed (2020). High Linearity Techniques for Analog Filters, Built-in Testing and Impedance Spectroscopy in Scaled CMOS Technologies. Doctoral dissertation, Texas A&M University. Available electronically from https : / /hdl .handle .net /1969 .1 /192711.
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