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dc.contributor.advisorKhatri, Sunil P
dc.creatorSharma, Kinshuk
dc.date.accessioned2021-01-12T16:58:14Z
dc.date.available2021-01-12T16:58:14Z
dc.date.created2016-08
dc.date.issued2016-08-08
dc.date.submittedAugust 2016
dc.identifier.urihttps://hdl.handle.net/1969.1/192025
dc.description.abstractMetastability causes unpredictable behavior in circuits, and can cause circuit failure. Any binary valued circuit element that holds state is vulnerable to metastability. Although the possibility of metastability cannot be completely eliminated in a circuit, the goal is to reduce it as much as possible. In this thesis, we discuss the design of a latch that effectively reduces metastability in circuits. In today’s SoC designs, different clock domains are often used for different functional units. If the clock domains are not synchronous, synchronizers are required for data crossing clock domains. A traditional synchronizer consists of 2 regular flip- flops and is not suited for high frequency operation. In this thesis, we present a new synchronizer design for high performance applications. The master as well as slave latches in the first flip-flop of this synchronizer use the metastability reducing latch. This latch has independent paths for the pull-up and pull-down transitions, thereby minimizing the possibility of metastability. Experimental results demonstrate a significant improvement in signal integrity compared to the traditional synchronizer. Our synchronizer also achieves an improvement in the worst case clock-to-output delay. Metastability in asynchronous designs has not been given significant attention and metastability resolution is assumed to be handled by the handshaking protocol. However, metastability might manifest (at the electrical level) in various asynchronous circuit elements. One such asynchronous circuit element susceptible to metastability is the C-element. The C-element is vulnerable to metastability conditions at its output, for a short overlap in the input values. In this thesis, a robust design of a C-element is proposed based on our metastability reducing latch. Three popular circuit topologies for a C-element have been studied and modified with the proposed approach. Experimental results show significant improvements in signal integrity, with up to 9× improvement in the metastability window.en
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectmetastabilityen
dc.subjectsynchronizeren
dc.subjectC-elementen
dc.titleDesign and Implementation of a Metastability Tolerant Latchen
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberLi, Peng
dc.contributor.committeeMemberKim, Eun Jung
dc.type.materialtexten
dc.date.updated2021-01-12T16:58:15Z
local.etdauthor.orcid0000-0002-0610-9918


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