Evaluation of L1 Residence for Perceptron Filter Enhanced Signature Path Prefetcher
Abstract
Rapid advancement of integrated circuit technology described by Moore’s Law has greatly increased computational power. Processors have taken advantage of this by increasing computation rates, while memory has gained increased capacity. As processor operation speeds have greatly exceeded memory access times, computer architects have added multiple levels of caches to avoid penalties for repeat accesses to memory. While this is an improvement, architects have further improved access efficiency by developing methods of prefetching data from memory to hide the latency penalty usually incurred on a cache miss. Previous work at Texas A&M and their submission to the Third Data Prefetching Championship (DPC3) primarily consisted of L2 cache prefetching. L1 prefetching has been less explored than L2 due to hardware limitations on implementation. In this paper, I attempt to evaluate the effect of L1 residence for Texas A&M’s Perceptron Filtered Signature Path Prefetcher (PPF). While an unoptimized movement of the PPF from the L2 to the L1 showed performance degradation, optimizations such as using the L1 data stream to prefetch to all cache levels and updating table sizes and lengths have matched L2 performance.
Subject
Data PrefetchingPrefetcher
Signature Path
Perceptron Filter
L1 Resident
L1 Residence
DPC3
Third Data Prefetching Championship
Citation
Staggs, Alexander (2020). Evaluation of L1 Residence for Perceptron Filter Enhanced Signature Path Prefetcher. Undergraduate Research Scholars Program. Available electronically from https : / /hdl .handle .net /1969 .1 /188383.