Method for fabricating a heterojunction schottky gate bipolar transistor
Abstract
Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region.
Subject
H01L 31/1105H01L 31/03046
H01L 31/03529
H01L 31/035263
H01L 31/1844
H01L 31/1127
H01L 29/739
H01L 31/1121
H01L 31/035209
H01L 29/205
H01L 31/11
Y02P 70/50
Collections
Citation
Ratcha, Aditya Chandra Sai; Verma, Amit; Nekovei, Reza; Khader, Mahmoud M. (2018). Method for fabricating a heterojunction schottky gate bipolar transistor. United States. Patent and Trademark Office; Texas A&M University. Libraries. Available electronically from https : / /hdl .handle .net /1969 .1 /177234.