dc.creator | Yoneda, Hideki | |
dc.creator | Sanchez-Sinencio, Edgar | |
dc.date.accessioned | 2019-06-17T16:54:53Z | |
dc.date.available | 2019-06-17T16:54:53Z | |
dc.date.issued | 1997-05-06 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/176561 | |
dc.description.abstract | The invention provides a pattern recognition processing apparatus and a technique for realizing a neural network of a complex structure within the processing apparatus. The apparatus includes a neural network having two-dimensional layers connected to form a feed-forward systolic array. Each two dimensional layer includes a feature extraction layer connected with a positional error absorbing layer. A host system provides inputs to the network. Each layer within the network includes processing elements such as a MOS analog circuit that receives input voltage signals and provides output voltage signals. | en |
dc.language | eng | |
dc.publisher | United States. Patent and Trademark Office | |
dc.rights | Public Domain (No copyright - United States) | en |
dc.rights.uri | http://rightsstatements.org/vocab/NoC-US/1.0/ | |
dc.title | Neural network processor including systolic array of two-dimensional layers | en |
dc.type | Utility patent | en |
dc.format.digitalOrigin | reformatted digital | en |
dc.description.country | US | |
dc.contributor.assignee | Kawasaki Steel Corporation | |
dc.contributor.assignee | The Texas A&M University System | |
dc.identifier.patentapplicationnumber | 08/542832 | |
dc.subject.uspcprimary | 706/31 | |
dc.subject.uspcother | 706/38 | |
dc.date.filed | 1995-10-13 | |
dc.publisher.digital | Texas A&M University. Libraries | |
dc.subject.cpcprimary | G06K 9/00986 | |
dc.subject.cpcprimary | G06N 3/0635 | |
dc.subject.cpcprimary | G06N 3/063 | |
dc.subject.cpcprimary | G06K 9/4628 | |