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dc.creatorYoneda, Hideki
dc.creatorSanchez-Sinencio, Edgar
dc.date.accessioned2019-06-17T16:54:53Z
dc.date.available2019-06-17T16:54:53Z
dc.date.issued1997-05-06
dc.identifier.urihttps://hdl.handle.net/1969.1/176561
dc.description.abstractThe invention provides a pattern recognition processing apparatus and a technique for realizing a neural network of a complex structure within the processing apparatus. The apparatus includes a neural network having two-dimensional layers connected to form a feed-forward systolic array. Each two dimensional layer includes a feature extraction layer connected with a positional error absorbing layer. A host system provides inputs to the network. Each layer within the network includes processing elements such as a MOS analog circuit that receives input voltage signals and provides output voltage signals.en
dc.languageeng
dc.publisherUnited States. Patent and Trademark Office
dc.rightsPublic Domain (No copyright - United States)en
dc.rights.urihttp://rightsstatements.org/vocab/NoC-US/1.0/
dc.titleNeural network processor including systolic array of two-dimensional layersen
dc.typeUtility patenten
dc.format.digitalOriginreformatted digitalen
dc.description.countryUS
dc.contributor.assigneeKawasaki Steel Corporation
dc.contributor.assigneeThe Texas A&M University System
dc.identifier.patentapplicationnumber08/542832
dc.subject.uspcprimary706/31
dc.subject.uspcother706/38
dc.date.filed1995-10-13
dc.publisher.digitalTexas A&M University. Libraries
dc.subject.cpcprimaryG06K 9/00986
dc.subject.cpcprimaryG06N 3/0635
dc.subject.cpcprimaryG06N 3/063
dc.subject.cpcprimaryG06K 9/4628


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