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A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform
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Approximate computing is a blooming field of research, which involves a compro- mise of an application’s accuracy to make it more efficient. It necessarily involves a deliberate effort to make an application imprecise in order to conserve some re- source. While the techniques for approximation may include using approximate functional units, approximate storage hardware, approximate network communica- tion or executing algorithms with varying precision, in this thesis, we mainly aim to use approximate arithmetic units in a JPEG Encoder Core. Using imprecise arithmetic units requires an identification of the applications which are resilient to errors. JPEG compression is inherently a lossy compression as the degradation in image quality isn’t perceptible to the end users for a significant compression ratio. This tolerance of JPEG compression to a loss of data is exploited to replace the accurate computationally intensive blocks of the JPEG encoding algo- rithm with their imprecise counterparts. The approximate hardware design proposed in this thesis is also reconfigurable, which implies that the end user can select the level of approximation desired based on the loss in accuracy allowed. The reconfigurable approximate JPEG hardware is also implemented on the FPGA platform. The FPGA emulation of the approximate and the precise ver- sions of the JPEG Encoder core is done on the Altera DE1-SoC with Cyclone V device and an ARM based Hard Processor System. The emulation provided a max- imum area reduction by 45%, maximum delay reduction by 29% and a maximum power reduction by 28% for an approximation of 8 least significant bits. For approx- imation of more than 8 least significant bits, the peak-signal-to-noise ratio of the decompressed image is very low, resulting in poor image quality.
Shrija, . (2016). A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform. Master's thesis, Texas A & M University. Available electronically from