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dc.contributor.advisorSánchez-Sinencio, Edgar
dc.creatorAlhassan, Nashiru
dc.date.accessioned2016-07-08T15:11:58Z
dc.date.available2018-05-01T05:48:47Z
dc.date.created2016-05
dc.date.issued2016-04-12
dc.date.submittedMay 2016
dc.identifier.urihttps://hdl.handle.net/1969.1/156935
dc.description.abstractWith integration of various functional modules such as radio frequency (RF) circuits, power management, and high frequency digital and analog circuits into one system on chip (SoC) in recent applications, power supply noise can cause significant system performance deterioration. This makes supply noise rejection of the embedded voltage reference crucial in modern SoC applications. Also the use of resistors in bandgap voltage references makes them less suitable for modern low power and portable applications. This thesis introduces two resistorless sub-1 V, all MOSFET references. The goal is to achieve a high power supply rejection (PSR) over a wide bandwidth not achieved in previous works. This high PSR over wide bandwidth is achieved by using a combination of a feedback technique and an innovative compact MOSFET low pass filter. The two references were fabricated in a standard 0.18 µm CMOS process. The first reference uses a composite transistor in subthreshold to produce a proportional-to-absolute temperature (PTAT) voltage which is converted to a current used to thermally compensate the threshold voltage of a MOSFET in saturation. The second references uses dynamic-threshold voltage MOSFET (DTMOS) to produce a PTAT voltage which is converted to a current used to thermally compensate the threshold voltage of a MOSFET in saturation. The measurement shows that both references consumes a sub-1 µW power across their entire operating temperatures. The first reference achieves a PSR better than 50 dB for frequencies of up to 70 MHz and a 20 ppm/°C temperature coefficient (TC) for temperatures from -35 °C — 80 °C. It has a compact area of 0.0180 mm2 and operates on a supply of 1.2 V — 2.3 V. The second reference achieves a PSR better than 50 dB for frequencies of up to 60 MHz. This reference achieves a TC of 9.33 ppm/°C after trimming for temperatures from -30 °C — 110 °C and a line regulation of 0.076 %/V for a step from 0.8 V to 2 V supply voltage with 360 nW power consumption at room temperature. It has a compact area of 0.0143 mm^2.en
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectvoltage referenceen
dc.subjecthigh PSRen
dc.subjectMOSFET referenceen
dc.subjectresistorlessen
dc.subjectbandgap referenceen
dc.titleLow Power, High PSR CMOS Voltage Referencesen
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorTexas A & M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberFink, Rainer J.
dc.contributor.committeeMemberEntesari, Kamran
dc.contributor.committeeMemberRusty Harris, Harlan
dc.type.materialtexten
dc.date.updated2016-07-08T15:11:58Z
local.embargo.terms2018-05-01
local.etdauthor.orcid0000-0001-9548-3655


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